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Hardware Design Considerations
Table 60. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required (continued)
GE2_SGMII_RX
GE2_SGMII_TX
GE2_SGMII_TX
GE2_TCK
GE2_TD[0–3]
GE2_TX_EN
Signal Name
Pin Connection
GND SXC
NC
NC
NC
NC
NC
3.4.4.3
GE1 and GE2 Management Pins
GE_MDC and GE_MDIO pins should be connected as required by the specified protocol. If neither GE1 nor GE2 is used (that
is, V DDGE2 is connected to GND), Table 61 lists the recommended management pin connections.
Table 61. Connectivity of GE Management Pins When GE1 and GE2 Are Not Used
GE_MDC
GE_MDIO
Signal Name
Pin Connection
NC
NC
3.4.5
UTOPIA/POS Related Pins
Table 62 lists the board connections of the UTOPIA/POS pins when the entire UTOPIA/POS interface is not used or subset of
UTOPIA/POS interface is used. For multiplexing options that select a subset of the UTOPIA/POS interface, use the connections
described in Table 62 for those signals that are not selected. Table 62 assumes that the alternate function of the specified pin is
not used. If the alternate function is used, connect that pin as required to support the selected function.
Table 62. Connectivity of UTOPIA/POS Related Pins When UTOPIA/POS Interface Is Not Used
UTP_IR
UTP_RADDR[0–4]
UTP_RCLAV_PDRPA
UTP_RCLK
UTP_RD[0–15]
UTP_REN
UTP_RPRTY
UTP_RSOC
UTP_TADDR[0–4]
UTP_TCLAV
UTP_TCLK
UTP_TD[0–15]
UTP_TEN
UTP_TPRTY
UTP_TSOC
V DDIO
Signal Name
Pin Connection
GND
V DDIO
NC
GND
GND
V DDIO
GND
GND
V DDIO
NC
GND
NC
V DDIO
NC
NC
3.3 V
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
73
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